This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating sub-lithographic semiconductor device features.
In general, semiconductor device scaling may be restricted by the current resolution limits of lithography technology. With the ongoing down-scaling of semiconductor devices and drive to increase feature density, Double Patterning Technology has been introduced as a solution to the resolution limits of current lithography equipment. Double Patterning Technology has allowed fabrication of device features beyond the lithographic printing limit utilizing a plurality masking, etch, and/or spacing techniques.
However, in the formation of metal device features, such as array wiring and connections between integrated circuitry, are highly sensitive to variations in uniformity and precision. Conventional Double Patterning Techniques may present problems in accuracy and uniformity. Thus the efficiency of conventional Double Patterning methods for such sensitive features is reduced.